`timescale  1ns/1ns
`default_nettype none

module pixel_display_buf_mbi6334
    #(
    parameter   DW      = 1
    )
    (
    // write
    input  wire         I_wclk,
    input  wire [DW-1:0]I_wren,
    input  wire [9:0]   I_waddr,
    input  wire [15:0]  I_wdata,
    // read
    input  wire         I_rclk,
    input  wire         I_rden,
    input  wire [13:0]  I_raddr,
    output wire [DW-1:0]O_rdata
    );
//***********************************************************
localparam  M = DW;

wire            rd_clk;
wire            rd_en;
wire [13:0]     rd_addr;
wire [DW-1:0]     q;

reg  [13:0]     raddr;

//***********************************************************
//-------------------------------------
// instance of dpram_256x1_256x1
//-------------------------------------
genvar i;
generate
    for(i=0;i<M;i=i+1)
    begin: gen_ram
        // swsr_512x1_512x1 data_buf (
        //   swsr_64x16_1024X1 data_buf(
        //   swsr_32x32_1024X1 data_buf(
        // swsr_64x16_1024X1 data_buf(
        swsr_1024x16_16384x1 data_buf(
            .clka   (I_wclk     ),
            // .ena    (1'b1       ),
            .wea    (I_wren[i]  ),
            .addra  (I_waddr    ),
            .dina   (I_wdata    ),
            .clkb   (rd_clk     ),
            .enb    (rd_en      ),
            .addrb  (rd_addr    ),
            .doutb  (q[i]       )
    );
    end
endgenerate
//***********************************************************

//raddr[9:0]
always@(posedge I_rclk)
    if(I_rden==1)
        raddr <= I_raddr;

//rd_clk
//rd_en
//rd_addr[11:0]
assign rd_clk  = I_rclk;
assign rd_en   = I_rden ;
assign rd_addr = I_raddr; 

//O_rdata[DW-1:0]
generate
    for(i=0;i<M;i=i+1)
    begin: gen_rdata_h
        assign O_rdata[i] = q[i];
    end
endgenerate
//***********************************************************
endmodule

`default_nettype wire

// vim:set ts=4 sw=4 et fenc=utf-8 fdm=marker:
